1. Field of the Invention
This invention is related to the field of microprocessors and, more particularly, to exception handling in multithreaded multiprocessors.
2. Description of the Related Art
Computer systems employing multiple processing units hold a promise of economically accommodating performance capabilities that surpass those of current single-processor based systems. Within a multiprocessing environment, rather than concentrating all the processing for an application in a single processor, tasks are divided into groups or xe2x80x9cthreadsxe2x80x9d that can be handled by separate processors. The overall processing load is thereby distributed among several processors, and the distributed tasks may be executed simultaneously in parallel. The operating system software divides various portions of the program code into the separately executable threads, and typically assigns a priority level to each thread.
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. As used herein, the term xe2x80x9cclock cyclexe2x80x9d refers to an interval of time accorded to various stages of an instruction processing pipeline within the microprocessor. Storage devices (e.g. registers and arrays) capture their values according to the clock cycle. For example, a storage device may capture a value according to a rising or falling edge of a clock signal defining the clock cycle. The storage device then stores the value until the subsequent rising or falling edge of the clock signal, respectively. The term xe2x80x9cinstruction processing pipelinexe2x80x9d is used herein to refer to the logic circuits employed to process instructions in a pipelined fashion. Although the pipeline may be divided into any number of stages at which portions of instruction processing are performed, instruction processing generally comprises fetching the instruction, decoding the instruction, executing the instruction, and storing the execution results in the destination identified by the instruction.
An important feature of microprocessors is the degree to which they can take advantage of parallelism. Parallelism is the execution of instructions in parallel, rather than serially. Superscalar processors are able to identify and utilize fine grained instruction level parallelism by executing certain instructions in parallel. However, this type of parallelism is limited by data dependencies between instructions. Further, as mentioned above, computer systems which contain more than one processor may improve performance by dividing the workload presented by the computer processes. By identifying higher levels of parallelism, multi-processor computer systems may execute larger segments of code, or threads, in parallel on separate processors. Because microprocessors and operating systems cannot identify these segments of code which are amenable to parallel multithreaded execution, they are identified by the application code itself. Generally, the operating system is responsible for scheduling the various threads of execution among the available processors in a multi-processor system.
Another important feature of microprocessors is the manner in which they handle exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted when dealing with exception or interruptions. In a multiprocessor computer, it may be desirable to hide the multiprocessor nature of the computer from the operating system in order to eliminate further overhead. However, hiding the nature of the system may itself result in additional overhead or incorrect operation.
The problems outlined above are in large part solved by a microprocessor and method as described herein. Additional circuitry is included which enables the handling of exceptions and interruptions in a multithreaded multiprocessor without revealing the multiprocessor nature of the computer to the operating system. Advantageously, additional overhead may be avoided and correct-handling of exceptions and interruptions may be attained.
Broadly speaking, a method of performing exception handling in a multiprocessor computer is contemplated. A first processor saves its state as a regular state and a second processor saves its state as a first extended state, in response to an exception of the first processor. In addition, control information is saved which includes an indication of which processor generated the exception. Finally, the exception is handled by the first processor.
In addition, a multiprocessor computer comprising a plurality of processors is contemplated. Included in the multiprocessor computer is circuitry to support multithreaded multiprocessing and a mapping table which is coupled to the processors. The mapping table includes exception handling circuitry which supports multithreaded multiprocessor exception handling.